Minutes of the meeting of the Panel on
Development, Manufacture and Export of IT Hardware
Date: 7th September,1998
Venue: Electronics Niketan, CGO Complex, New Delhi
A meeting of the Panel on Development, Manufacture and Export of IT Hardware of the National Task Force on Information Technology and Software Development was held under the Chairmanship of Secretary, Department of Electronics, on 7.9.1998 at Electronics Niketan, CGO Complex, New Delhi to discuss and firm up policy on Microelectronics and IT Process Industries. The list of participants is given in Annexure-I.
On the basis of the detailed discussions on the background reports and the set of draft recommendations available to the participants the following policy instruments are recommended:
1. For purposes of this policy the following definitions shall apply:
i. Microelectronics covers discrete semiconductor devices such as diodes, transistors, thyristors, as well as Integrated Circuits (ICs) ranging from Small Scale/Medium Scale ICs (SSI/MSI) to Large Scale/Very Large Scale ICs(LSI/VLSI) and, more recently System Level Integration/System-on-chip (SLI/SOC).
ii. The Microelectronics Manufacturing Unit (MMU) is a unit engaged in one or more of the following activities relating to the manufacture of discrete semiconductor devices as well as ICs:
Computer Aided Design (CAD) of discrete semiconductor devices as well as ICs.
Integrated device manufacturing as well as foundry activity involving the complete range of unit processes, starting from a base wafer to packaged and tested devices & ICs.
Assembly and packaging operation based on diffused wafers.
Testing of microelectronics products.
Technology CAD (TCAD).
Design, development and manufacture of capital equipment for the manufacture of discrete semiconductor devices as well as ICs.
iii. Megafab is an MMU engaged in integrated device manufacturing foundry operations with a total unit plant investment level of Rs.2000 crore and above.
II. Policy Package for Megafabs
2. Government will pro-actively invite major international companies to set up megafabs in the country by giving them appropriate incentives, and infrastructural facilities as well as removing all bottlenecks and simplifying procedures for maximising their velocity of business which will be comparable to international levels. Towards this end the following policy measures will be given:
i. All the policy instruments available to the S-BIT units will apply mutadis mutandis to the investments in the setting up and running of megafabs.
ii. Corporate Income Tax will be exempted for 10 years from the first day on which income is earned with permission to carry forward losses and deduct them as expenses up to 5 years. Where units are set up as S-BIT zones/habitats, 50% reduction of Income Tax for a further period of five years will be applicable.
iii. Dividends, if paid out, will be free from all taxes during the Corporate Income Tax exemption period in the hands of the investors or shareholders. Further, an investment allowance of 25% will be available for deduction from the taxable corporate Income.
iv. Compensation of training expenses including actual expenses, accommodation and transportation will be available through a cash grant.
v. Legally valid guarantees will be given against nationalisation, canalisation and State monopolisation.
vi. The movement of foreign specialists involved in making feasibility studies, setting up of facilities and assisting in the running of facilities shall be facilitated by simplified procedures administered by a single window which will give all clearances within 48 hours.
III. High Tech Parks
3. Government would encourage, build, subsidise high tech parks, separately or as a part of S-BIT zones/habitats, especially suited to microelectronics as defined earlier. Such parks would require inputs like high purity gases, abundant supply of good quality water, stable and quality power, high speed connectivity, cluster of support services for supporting megafabs etc. Fiscal measures for setting up of such parks are given below:
i) Exemption of Interest Tax under Sec 10(15)(iv) to be amended to include high tech park.
ii) Income Tax
a) for assessment purpose consider unsold units as business assets
b) Income on such assets be assessed on actual accruals and not on notional basis.
c) Depreciation, repairs be taken on actuals basis and not on notional basis.
iii) Business assets of high tech parks including residential units be exempted from wealth tax.
iv) ECB guidelines should be relaxed further. The average tenor of the loan is stipulated as 7 years without any option for prepayment. This needs to be reduced to an average tenor of 3 years with a provision for prepayment.
v) Domestic banking system should be encouraged to finance approved high tech parks and not consider them as a real estate activity. It may consider soft loans for these activities(interest burden could be offset by the Central and State Governments on a matching basis.)
vi) All imports such as captive power plant, data/communication infrastructure, testing laboratory equipment, effluent treatment plant, air-conditioning plant etc. required for setting up and running a high tech park typically consisting of industrial zone, R&D zone, housing zone, urban zone, amenity zone etc. shall be allowed at zero import duty.
vii) All purchase transactions will be free of Sales Tax, Entry Tax, Excise Duty, Purchase Tax/Trade Tax/Turnover Tax and Octroi.
viii) High tech parks should be recognised as eligible investments in infrastructure and therefore receive the benefit of nil tax under Section 80(I)(A) of the Income Tax Act.
ix) In addition, High tech parks would also be eligible for all the concessions/benefits/incentives for industrial parks as decided by the Government based on the "India Infrastructure Report - Policy Imperatives for Growth and Welfare" prepared by the Expert Group on the Commercialisation of Infrastructure Projects.
IV. R&D and Manpower Development
4. Continue supporting basic and applied research, technology development, manpower development at academic institutions, R&D laboratories and industry covering various facets of semiconductor technology including discrete devices, integrated circuits, CAD, software tools, capital equipment etc.
5. Develop Centres of Excellence on various facets of semiconductor technology e.g. system level integration/system on chip, application specific processor design, low power IC design, microelectromechanical systems applications development with a view to enhance microelectronics usage, power devices, III-V compounds, high speed testing etc.
6. Set up a National level institute/facility for taking process development at academic institutions and R&D laboratories closer to industrial acceptance by undertaking additional process & device structure research, trying out new process and device structure concepts, prototyping of new products, testing of discrete devices as well as ICs etc.
7. Strengthen and enhance the scope and contents of the manpower development programme in VLSI design & related software initiated by DOE to include, inter-alia, more institutions, upgrading and augmenting the CAD environment, short-term courses, workshops, seminars, conferences; CAD tools and related software development, marketing Indian competence abroad etc.
8. Launch 'India Chip" programme along the lines similar to MOSIS in USA and CMP in France to nurture microelectronic design ideas of students and researchers at academic institutions and R&D laboratories as well as in small and medium scale industries.
9. One IIIT should be set up a specialization in microelectronics
10. DOE should set up an advisory core group representing academic institutions, R&D laboratories and industry which would prepare model syllabi and also address teacher training needs.
V. Institutional Mechanism
11. To implement the measures and programmes outlined above covering a proactive approach for attracting investments in Megafabs, catalysing setting up of High Tech Parks, R&D and manpower development, as well as encouraging and supporting the domestic microelectronics industry to improve economy of scale, upgradation of technology; catalysing the setting up of world-class assembly, packaging, testing units as well as any other measures and programmes that are felt desirable to promote the microelectronics industry and attract investments in this sector, an appropriate institutional mechanism along the lines similar to EDB, Singapore with a national corpus fund of Rs.4000 Crores would be set up. The disbursement of this corpus fund would be, among other modalities, in the form of one third matching investment as soft loans/equity/venture capital/cash grants to a similar one third matching investment by the State Government and one third investment by the MMU/Company.
B. PROCESS INDUSTRIES
12. For Process Industries manufacturing components, all the policy instruments available under (2), (3), (4), (5) and (6) will correspondingly apply.
List of participants attended the meeting held on 7.9.1998 at 11.00 a.m. under the Chairmanship of Secretary, Department of Electronics.
Representatives of Government
1. Shri Ravindra Gupta, Secretary, DOE (Chairperson)
2. Dr.N.Seshagiri, Spl.Secretary, Planning Commission & DG, NIC
and Member Convener, National Task force on IT &SD
3. Shri O.N.Vaid, JS, DOE
4. Shri G.Soni, Adviser, DOE
5. Dr.U.P.Phadke, Sr.Director, DOE
6. Shri V.Dharmadhikari, Sr.Director, DOE
7. Shri R.S.Buttoo, Director, DOE
8. Shri R.C.Sachdeva, Director, DOE
9. Shri D.Choudhry, Director, DOE
10. Shri Debashis Dutta, Additional Director, DOE
11. Maj.Gen.Davinder Kumar, Additional DG(Telecom), Army HQ.
12. Col.S.C.Sharma, Army HQ
13. Shri V.Sivasubramanian, Technical Officer, Min. of Finance
14. Shri T.K.Shah, Director, CBDT, Min. of Finance
15. Ms.Anuradha Balram, Min. of Finance
Representatives of Industry
1. Dr.M.J.Zarabi, CMD, SCL, Chandigarh
2. Shri R.Ranganath, GM, BEL, Bangalore
3. Shri K.P.Raghunath, DGM, BHEL, Bangalore
4. Shri Inderdeep Singh, President, ELCINA
5. Shri N.Kohli, Vice-President, Electronics & Software Export
6. Shri Vinnie Mehta, Director, MAIT
7. Shri Ajai Chowdhry, CEO, HCL Infosystems
8. Shri Jaswinder Ahuja, Vice-President, Cadence
9. Shri Saugat Sen, Director(Engineering), Cadence
10. Shri Vinay Deshpande, NCORE, Bangalore
11. Shri.Mario Santi, SGS-Thomson, NOIDA